1. Field of the Invention
The present invention relates to a semiconductor memory device. Particularly, the present invention relates to a semiconductor memory device having a redundancy memory cell array.
2. Description of the Related Art
Generally, the conventional semiconductor memory device is provided with a row control circuit, a row address buffer, a row decoder and driver, a regular memory cell array, a sense amplifier, a column address buffer, a column decoder, and so on. A row address strobe signal (RAS) is input to the row control circuit from the external, and the row control circuit supplies control signals to the row address buffer and the row decoder and driver at a predetermined timing, respectively.
When the potential level of the signal RAS becomes low, the control signal is supplied from the row control circuit to the row address buffer. The row address buffer then supplies row address bit signals to the row decoder and driver, and when the potential levels of the row address bit signals output from the row address buffer have been established, the control signal is supplied from the row control circuit to the row decoder and driver. The row decoder and driver then select a predetermined word line, and the potential thereof is raised in accordance with the potential levels of the input row address bit signals.
Thus, in the read mode, data stored in a predetermined memory cell arranged at the intersection of the selected word line and a selected bit line provided in the regular memory cell array is read out through the selected bit line, sense amplifier, and data bus provided in the column decoder. Also, in the write mode, predetermined data is written from the external to the predetermined memory cell connected to the selected word line through the data bus and the selected bit line.
In this connection, the column decoder selects a predetermined bit line in accordance with potential levels of the input column address bit signals supplied from the column address buffer.
Also, known is a conventional semiconductor memory device having a redundancy memory cell array in addition to the regular memory array. Provided in such a memory device are, a programming circuit for programming the defective address bits corresponding to a defective memory cell existing in the regular memory cell array, a comparison circuit for comparing each logic of the input address bits (for example, input row address bit signals) with each of the programmed defective address bits and for detecting whether or not each logic of the input row address bits coincides with each of the programmed address bits, and a switching circuit for supplying control signals to the row decoder and driver for the regular memory cell array and for the redundancy memory cell array, respectively, in accordance with the result of the above comparison.
Accordingly, when the potential levels of the row address bit signals output from the row address buffer have been established, a control signal is supplied from the row control circuit to the comparison circuit. The comparison circuit then, compares each logic of the input row address bits with each logic of the defective address bits programmed in the programming circuit, and an output signal having a predetermined potential level is supplied from the comparison circuit to the switching circuit in accordance with the result of the comparison.
Further, when the potential level of the output signal from the comparison circuit has been established, a control signal is supplied from the row control circuit to the switching circuit, and the switching circuit carries out a switching operation in accordance with the logic of the output signal from the comparison circuit.
Namely, when the comparison circuit detects that at least one logic of the input row address bits does not coincide with the corresponding defective row address bit programmed in the programming circuit, the potential of the output signal from the comparison circuit becomes low level, for example, and when the potential level of the output signal from the comparison circuit has been set to low level, the above control signal from the row control circuit is supplied through the switching circuit to the row decoder and driver, to select a predetermined word line provided in the regular memory cell array in accordance with the potential levels of the input row address bit signals. Thus, data stored in a predetermined memory cell arranged at the intersection of the selected word line and the selected bit line provided in the regular memory cell array is read out, or predetermined data is written from the external to the predetermined memory cell.
On the other hand, when the comparison circuit detects that each logic of the input row address bits coincides with each of the defective row address bits programmed in the programming circuit, the potential of the output signal from the comparison circuit becomes high level, for example, and when the potential level of the output signal from the comparison circuit has been set to high level, the above control signal from the row control circuit is supplied through the switching circuit to the redundancy row decoder and driver, to select a predetermined redundancy word line provided in the redundancy memory cell array in accordance with the input row address bit signals corresponding to the programmed defective address bits.
Accordingly, data stored in a predetermined redundancy memory cell arranged at the intersection of the selected redundancy word line and the selected bit line provided in the redundancy memory cell array is read out, or predetermined data is written from the external to the predetermined redundancy memory cell. At this time, the word line corresponding to the defective row address bits provided in the regular memory cell array is in the non-selected state.
As above-mentioned, in the memory device having the redundancy memory cell array, the time required for selecting a predetermined word line provided in the regular memory cell array or the redundancy memory cell array is delayed by the time required for establishing the potential level of the output signal supplied from the comparison circuit to the switching circuit, compared with the time required for selecting a predetermined word line provided in the regular memory cell array in the memory device not having the redundancy memory cell array.
Therefore, in a conventional memory device having the redundancy memory cell array, a problem arises in that, even if a defective memory cell does not exist in the regular memory cell array and the redundancy memory cell array is not used (i.e., even if defective address bits are not programmed in the programming circuit), the operation timing for selecting a predetermined word line provided in the regular memory cell array (i.e., the access timing for a selected memory cell connected to the selected word line) is delayed by the above-mentioned time, compared with the corresponding timing in the memory device not having the redundancy memory cell array.